Conventionally, there has been a technology of determining by a formal verification of whether a terminal indicated as being open in circuit information indicating a semiconductor integrated circuit is open in a design specification or open due to a design error (see, e.g., Japanese Laid-Open Patent Publication No. 2011-203962).
Further, there has been a technology of confirming that the state of an input terminal specified to have a fixed value does not enter a high-impedance state and, when not in the high-impedance state, determining by simulation whether the value of the input terminal becomes an anticipated value (see. e.g., Japanese Laid-Open Patent Publication No. 2009-48312).
Conventionally, in semiconductor integrated circuit testing, there has been a technology of sending a test signal to verify a connection part between open terminals and testing validity of an inter-macro connection by monitoring this test signal (see, e.g., Japanese Laid-Open Patent Publication No. H10-326301).
Nonetheless, there is a problem in that whether a specific terminal has become an open terminal in the circuit information cannot be determined by simulation and as a result, verification related to the terminal connection cannot be performed efficiently.